
Sleepy Dwarf’s Somniloquy on Drowsy Logic Chip Design
02-2024 Download Paper An abbreviated edition was published on EENews (02-23-2024) Abstract Power-efficiency has been an increasing design consideration in virtually all new silicon in the past 15 years. Power-first designs, however, typically appear only in niche applications such as IoT. A 2023 retrospective paper of a research lab’s 2002 circuit, using a technique called “drowsy logic,” reviewed historical strategies to limit leakage in the context of foundries’ recent implementation of low-leakage FinFET and Gate-All-Around technologies....